1. Field of the Invention
The present invention relates to a digital phase locked loop for use with integrated circuits such as ASIC (application specific integrated circuits) chips.
2. Description of the Related Art
In a prior art digital phase locked loop, the reference clock pulse is delayed by a variable delay line in the amount corresponding to the output of an up-down counter, which counts the reference clock. The delayed clock is fed into a clock tree where it propagates through different paths to the outputs of the clock tree and is applied to the various parts of an LSI chip. One of the outputs of the clock tree is applied to a phase detector where it is compared with the reference clock. The output of the phase detector is applied as an up/down command input to the up-down counter, which, in response, increments or decrements its count value. However, the prior art PLL suffers from jitter produced as a result of the variation of delays introduced to the reference clock. Additionally, if the magnitude of jitter is restrained to within limited bounds, the upper limit of the lock range of the PLL would be constrained by the delay time of the clock tree.